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Synchronous Memory Elements - Operation
Synchronous Memory Elements - Operation
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Signal and Timing Parameters I Common Clock – Class 2

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1Signal and Timing Parameters I Common 14delays in order to avoid logic errors.
Clock – Class 2. Acknowledgements: Intel (We’ll cover this in more detail
Bus Boot Camp: Howard Heck. Prerequisite shortly.). Signal Parameters & Timing
Reading assignment: CH8 to 9.3. Class 2. Transmit clock at device a.
2Agenda. Voltage and Time Budgets Receive clock at device b.
Computer Signaling Elements and Circuits 15Sources of Clock Skew. Clock skew is
Flight time Synchronous Bus Operation caused by: variation between the clock
Clock Skew and Jitter Setup and Hold driver circuits in a given part (Tdrv).
Manufacturing Considerations Advanced variation in the loading between different
Topics. Signal Parameters & Timing agents on the bus (CL). variation in
Class 2. interconnect characteristics (Z0, td ).
3Voltage and time. SI boils down to variation in electrical lengths. What is
meeting voltage and time specifications electrical length? Signal Parameters &
True for most I/O computer interfaces Timing Class 2.
Violating a time or voltage specification 16Clock Jitter. Cycle to cycle variation
i.e. exceeding a limit, may cause a of clock Changes the time available for
circuit to fail Notice the use of the word data to get from transmitter to receiver
“may” rather than “will” Most limits are Jitter + Skew = Clock uncertainty for
at least 3 sigma limits. The actual sigma setup Skew = Clock uncertainty for hold
limits are usually a company secret. Hold uses same cycle of clock In many
Margin is the difference between a cases we can ignore certain types of
specification and the respective measured jitter There are other types of jitter –
signal parameter. Margin is considered a more advanced topic. Signal Parameters
quality factor for a design. Signal & Timing Class 2. Idea clock. Clock
Parameters & Timing Class 2. with Cycle to Cycle Jitter. Bar graph of
4SI Budgets. An SI budget is a each cycle time. Pulse Width. Pulse Width.
technique used to report timing and (Ideal). (Actual).
voltage margin in terms of voltage and 17Skew & Jitter Example. 100 MHz bus
timing components (“buckets”) for all Minimum clock period = 10 ns Given:
configurations and conditions of a Maximum skew = 250 ps Maximum edge-edge
particular bus design. The budget is often jitter = 250 ps. Calculate the minimum
represented in a spread sheet. effective clock period: minimum effective
=B2-(C2+D2+E2) … Cell formula. Signal period = minimum period – maximum skew –
Parameters & Timing Class 2. maximum jitter min effective period = 10.0
5What Failing SI Means: Negative ns – 0.25 ns – 0.25 ns = 9.5 ns Therefore,
margin. + limit. - limit. Mean. The maximum allowed for silicon plus
integral of the probability function interconnect delay is 9.5 ns. Signal
outside these limits is the failing Parameters & Timing Class 2.
population Pf X volume X cost/unit = 18Setup Timing Diagram & Loop
variable cost of failure Not the whole Analysis. Tcycle. Signal Parameters &
story – A bad name can cost billions in Timing Class 2.
fixed costs (good will). Probability that 19Hold Timing Equation. Uses same clock
a parameter is a certain value. Measured edge Hold equation Define Clock Delay
parameter value. Signal Parameters & Clock Skew Simplify. Signal Parameters
Timing Class 2. & Timing Class 2.
6Simple I/O Architecture. Pre- ’00 the 20Manufacturability Considerations.
most common computer I/O interface was Sources of variability in silicon:
synchronous memory transfer Intel Xeon 100 manufacturing process (e.g. silicon gate
MHz bus was just about the last in this length) operating temperature (MOS speed ?
class Clock distribution is a challenge – as temp ?) operating voltage (MOS speed ?
more on this later. CPUs. clock. RAM as voltage ?) Impact: variability leads to
Memory & I/O control. Signal a range of values for driver and receiver
Parameters & Timing Class 2. timings Example: Pentium® Pro GTL+ timings
7Synchronous Memory Elements - Minimum driver valid delay = 0.55 ns
Operation. Operation A data signal (in) Maximum driver valid delay = 4.40 ns
that is present at the input to the Maximum receiver setup time = 2.20 ns
flip-flop is “latched” into the flip-flop Maximum receiver hold time = 0.45 ns
by the rising edge of the input clock Sources of interconnect variability:
signal (clk). On the next rising edge of Manufacturing variation (Z0, er) Trace
clk, the data signal is released to the length variation (among 144 signals for
output of the flip-flop (out). This means FSB, for example). Signal Parameters &
data is clocked out of device a on one Timing Class 2.
clock edge and received at device b on the 21Revised Timing Equations. Setup.
next clock edge. This is also called Product specifications must comprehend the
common clocking. Signal Parameters & expected variation. We need to modify the
Timing Class 2. setup & hold equations: The setup
8Synchronous Memory Elements - Timing. equation defines the minimum clock cycle
Timing Valid data must be present for a time (max frequency) in terms of the
minimum amount of time prior to the input maximum system delay terms. We want
clock edge to guarantee successful capture Tmargin_setup ? 0. Excessive system delays
of the data. This is known as setup time, can be handled by increasing cycle time,
Tsetup. Data must remain valid for a at the cost of reduced performance. The
minimum amount of time after the input hold equation defines minimum system delay
clock edge to guarantee that the proper requirements to avoid logic errors due to
value is captured. This is called hold hold violations. We want Tmargin_hold ? 0.
time, Thold. Signal Parameters & Minimum delay violations cannot be fixed
Timing Class 2. by increasing cycle time. Why? Signal
9Simple Flight Time Concept. Connection Parameters & Timing Class 2.
Trace. Device a. Device b. The time it 22Device Specs and Test Loads. System.
takes a signal to travel from device a to Spec Load. Device specifications vs.
device b or the delay between transmitted system conditions The manufacturer
(a) and received (b) signals. This is not guarantees that the parts meet the values
the definition that SI engineers use in a in the timing specifications when driving
timing budget There are issues with timing into the “spec load”. This is really the
budgets and device timing parameters that only way devices can be tested. The spec
make this a poor definition. We will load is typically equal to the load
develop the exact definition of flight presented to the device by the device
time for SI later SI engineers use the level test environment. This spec load is
term propagation delay but it is not the generally not the same as the load
same as AC propagation delay. We will presented to the device by the system
develop the exact definition later; for interconnect. W. 65. 10pF. Signal
now let’s consider all delays the same. AC Parameters & Timing Class 2.
is frequency domain analysis. Signal 23Impact of Spec Loads. Since the spec
Parameters & Timing Class 2. load is NOT equal to the load on the
10Synchronous Bus Operation. Explain device when placed in a system: An output
picture? clk. a. b. We wish to use the buffer will have a different delay in the
clock to control the transmission of data system than in the test environment. To
from the latch in the source (a) to the deal with this: define new timing terms
latch in the destination (b). The initial change the way we break the timings into
clock pulse causes the source latch to separate components. Signal Parameters
release the data onto the interconnect. & Timing Class 2.
The next clock pulse causes the 24Flight Time. Tco. Voltage. Time.
destination latch to capture the data that Tflight. Tdrv. Tprop. Threshold. Driver
was transmitted on the interconnect We Pin into System Load. Clock Input to
have 1 full clock cycle to get the data Transmitting Chip. Driver Pin into Test
from the source to destination. Signal Load. Receiver Pin. Signal Parameters
Parameters & Timing Class 2. CLK. CLK. & Timing Class 2.
CORE. CORE. FROM. TO. Q. Q. D. D. 25Flight Time Explained. Define Tco
11Transmit Clock Sequence. Initial (time from clock-in to data-out) as the
(driving) clock pulse transmission from delay from the input clock to the output
clock generator to source. Tdrv_clk = data when driving into the test load.
delay of the clock buffer circuit Define Tflight (flight time) as the delay
connected to the source from node 1 to to the receiver minus the Tco. By defining
node 1a. Tprop_clk = delay of the the timings in this way, the flight time
interconnect between clk & a. clk. a. accounts for the propagation delay of the
b. (1). T. (1a). T. (1b). Signal interconnect PLUS the difference between
Parameters & Timing Class 2. drv_clk. the driver delays when driving test load
prop_clk. CLK. CLK. CORE. CORE. FROM. TO. vs. the system load. Notice: We defined
Q. Q. D. D. Tco and Tflight this way to guarantee the
12Data Path Sequence. Data transmission overall system timings remain the same.
from source to destination. Tdrv = delay Signal Parameters & Timing Class 2.
of the output buffer circuit for the data 26Revised Timing Equations. The system
signal. Tprop = interconnect delay between designer relies on the synchronous timing
source and destination. Tsetup = delay of equations help define the working flight
the input buffer plus the flip-flop setup time window (min-to-max) with the given
requirement. clk. a. b. (1). T. T. T. T. component timing specs. Ultimately, the
(1a). T. (1b). (2b). (2a). (2c). Signal equations provide a tool for a design
Parameters & Timing Class 2. prop. team. Use them to evaluate design
CLK. CLK. CORE. CORE. FROM. TO. Q. Q. D. trade-offs in order to achieve system
D. drv. setup. drv_clk. prop_clk. performance (frequency) targets. Signal
13Receive Clock Sequence. Second Parameters & Timing Class 2.
(receiving) clock pulse transmission from 27Example: Bus Timing Spread Sheet –
clock generator to destination. Setup times. Signal Parameters &
Tdrv_clk(b) = delay of the clock buffer Timing Class 2.
circuit connected to b. Tprop_clk(b) = 28Synchronous Timing Summary.
delay of the interconnect between clk Synchronous memory elements require a
& b. Ideal assumption: Tdrv_clk = stable data signal for a minimum amount of
Tdrv_clk(b) & Tprop_clk = time prior to (SETUP) & after (HOLD)
Tprop_clk(b). clk. a. b. (1). T. T. (b). the input clock. Hold and setup conditions
(3a). (1a). T. T. (b). (1b). (3b). T. determine the minimum and maximum system
(2b). T. T. (2a). (2c). Signal Parameters delays. Setup and hold conditions can be
& Timing Class 2. CLK. CLK. CORE. analyzed by constructing timing loops in
CORE. FROM. TO. Q. Q. D. D. drv_clk. the timing diagrams. Component delays
drv_clk. prop_clk. prop_clk. prop. drv. exhibit variation across process and
setup. environmental conditions. Interconnect
14Clock Skew. What happens if the clock delays vary due to design and process.
signals at the source and destination are Redefining driver and interconnect delays
not in phase? What if the clock arrives at in terms of system and “spec” loads allows
the destination before it reaches the manufacturers to specify and test
source? Vice-versa? What are the sources component delays. System timing equations
of uncertainty in the phase relationship provide a key tool for examining
between different clock signals? Clock trade-offs during system design. Signal
Skew: pin-to-pin variation in the timing Parameters & Timing Class 2.
of input clock at each agent (source & 29Assignment. Create Budget Spreadsheet
destination, in our example) on a bus. The for setup and hold Find and justify
net effect of clock skew is that it can maximum frequency of operation Find all
reduce the total delay that signals are minimum lengths. CPU1. CPU4. CPU2. CPU3.
allowed to have for a given frequency L1=5”. L4=3”. L3=2”. Chipset. L2=2”.
target. require larger minimum signal Signal Parameters & Timing Class 2.
Signal and Timing Parameters I Common Clock – Class 2.ppt
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