Тексты на английском
<<  Department of Computer Science & Engineering ART between the Wars  >>
Superscalar Processors vs
Superscalar Processors vs
Emergence and spread of superscalar processors
Emergence and spread of superscalar processors
Evolution of superscalar processor
Evolution of superscalar processor
Specific tasks of superscalar processing
Specific tasks of superscalar processing
Parallel decoding {and Dependencies check}
Parallel decoding {and Dependencies check}
The principle of perdecoding
The principle of perdecoding
Number of perdecode bits used
Number of perdecode bits used
7.3 Superscalar instruction issue
7.3 Superscalar instruction issue
Issue policies
Issue policies
Instruction issue policies of superscalar processors: ---Performance,
Instruction issue policies of superscalar processors: ---Performance,
Issue rate {How many instructions/cycle}
Issue rate {How many instructions/cycle}
Issue stopped by True dependency
Issue stopped by True dependency
Issue order of instructions
Issue order of instructions
Aligned vs
Aligned vs
Direct Issue
Direct Issue
The principle of shelving: Indirect Issue
The principle of shelving: Indirect Issue
Design space of shelving
Design space of shelving
Scope of shelving
Scope of shelving
Layout of shelving buffers
Layout of shelving buffers
Implementation of shelving buffer
Implementation of shelving buffer
Basic variants of shelving buffers
Basic variants of shelving buffers
Using a combined buffer for shelving, renaming, and reordering
Using a combined buffer for shelving, renaming, and reordering
Number of shelving buffer entries
Number of shelving buffer entries
7.4.4 Operand fetch policies
7.4.4 Operand fetch policies
Operand fetch during instruction issue
Operand fetch during instruction issue
Operand fetch during instruction dispatch
Operand fetch during instruction dispatch
7.4.5 instruction dispatch scheme
7.4.5 instruction dispatch scheme
Dispatch policy: Dispatch order
Dispatch policy: Dispatch order
-Dispatch rate (instructions/cycle)
-Dispatch rate (instructions/cycle)
Maximum issue rate <= Maximum dispatch rates >> issue rate reaches max
Maximum issue rate <= Maximum dispatch rates >> issue rate reaches max
- Scheme for checking the availability of operands: The principle of
- Scheme for checking the availability of operands: The principle of
Schemes for checking the availability of operand
Schemes for checking the availability of operand
Use of multiple buses for updaing multiple individual reservation
Use of multiple buses for updaing multiple individual reservation
Interal data paths of the powerpc 604
Interal data paths of the powerpc 604
-Treatment of an empty reservation station
-Treatment of an empty reservation station
Example overview
Example overview
Cycle i: Issue of the ‘mul’ instruction into the reservation station
Cycle i: Issue of the ‘mul’ instruction into the reservation station
Cycle i+1: Checking for executable instructions and dispatching of the
Cycle i+1: Checking for executable instructions and dispatching of the
Cycle i+1 (2nd phase): Issue of the subsequent two ‘ad’ instructions
Cycle i+1 (2nd phase): Issue of the subsequent two ‘ad’ instructions
Cycle i+2: Checking for executable instruction (mul not yet completed)
Cycle i+2: Checking for executable instruction (mul not yet completed)
Cycle i+3: Updating the FX register file with the result of the ‘mul’
Cycle i+3: Updating the FX register file with the result of the ‘mul’
Cycle i+3 (2nd phase): Checking for executable instructions and
Cycle i+3 (2nd phase): Checking for executable instructions and
Choronology of introduction of renaming (high complexity, Sparc64 used
Choronology of introduction of renaming (high complexity, Sparc64 used
Static or Dynamic Renaming
Static or Dynamic Renaming
>Design space of register renaming
>Design space of register renaming
-Scope of register renaming
-Scope of register renaming
-Layout of rename buffers
-Layout of rename buffers
-Type of rename buffers
-Type of rename buffers
-Number of rename buffers
-Number of rename buffers
-Basic mechanisms used for accessing rename buffers
-Basic mechanisms used for accessing rename buffers
Structure of the rename buffers and their supposed initial contents
Structure of the rename buffers and their supposed initial contents
Allocation of a new rename buffer to destination register (circular
Allocation of a new rename buffer to destination register (circular
Accessing abailable register values
Accessing abailable register values
Accessing a register value that is not yet available
Accessing a register value that is not yet available
Re-allocate of r2 (a destination register)
Re-allocate of r2 (a destination register)
Updating the rename buffers with computed result of {mul r2, r0, r1}
Updating the rename buffers with computed result of {mul r2, r0, r1}
Deallocation of the rename buffer no
Deallocation of the rename buffer no
Sequential consistency models
Sequential consistency models
Principle of the ROB {Circular Buffer}
Principle of the ROB {Circular Buffer}
Introduction of ROBs in commercial superscalar processors
Introduction of ROBs in commercial superscalar processors
Design space of ROBs
Design space of ROBs
Basic layout of ROBs
Basic layout of ROBs
ROB implementation details
ROB implementation details
Sequential consistency of exception processing
Sequential consistency of exception processing
The peinciple of superscalar CISC execution using a superscalar RISC
The peinciple of superscalar CISC execution using a superscalar RISC
PentiumPro: Decoding/converting CISC instructions to RISC operations
PentiumPro: Decoding/converting CISC instructions to RISC operations
Case Studies: R10000 Core part of the micro-architecture of the R10000
Case Studies: R10000 Core part of the micro-architecture of the R10000
Case Studies: PowerPC 620
Case Studies: PowerPC 620
Case Studies: PentiumPro Core part of the micro-architecture
Case Studies: PentiumPro Core part of the micro-architecture
PentiumPro Long pipeline: Layout of the FX and load pipelines
PentiumPro Long pipeline: Layout of the FX and load pipelines
Картинки из презентации «TECH Computer Science» к уроку английского языка на тему «Тексты на английском»

Автор: . Чтобы познакомиться с картинкой полного размера, нажмите на её эскиз. Чтобы можно было использовать все картинки для урока английского языка, скачайте бесплатно презентацию «TECH Computer Science.ppt» со всеми картинками в zip-архиве размером 9495 КБ.

TECH Computer Science

содержание презентации «TECH Computer Science.ppt»
Сл Текст Сл Текст
1TECH Computer Science. Superscalar 66associative access (latter e.g.) Rename
Processors. 7.1 Introduction 7.2 Parallel buffers with indexed access (always
decoding 7.3 Superscalar instruction issue corresponds to the most recent instance of
7.4 Shelving 7.5 Register renaming 7.6 renaming).
Parallel execution 7.7 Preserving the 67-Operand fetch policies and Rename
sequential consistency of instruction Rate. rename bound: fetch operands during
execution 7.8 Preserving the sequential renaming (during instruction issue)
consistency of exception processing 7.9 dispatch bound: fetch operand during
Implementation of superscalar CISC dispatching Rename Rate the maximum number
processors using a superscalar RISC core of renames per cycle equals the issue
7.10 Case studies of superscalar rate: to avoid bottlenecks.
processors. CH01. 687.5.8 Detailed example of renaming.
2Superscalar Processors vs. VLIW. renaming: mul r2, r0, r1 ad r3, r1, r2 sub
3Superscalar Processor: Intro. Parallel r2, r0, r1 format: op Rd, Rs1, Rs2 Assume:
Issue Parallel Execution {Hardware} separate rename register file, associative
Dynamic Instruction Scheduling Currently access, and operand fetching during
the predominant class of processors renaming.
Pentium PowerPC UltraSparc AMD K5- HP 69Structure of the rename buffers and
PA7100- DEC ? their supposed initial contents. Latest
4Emergence and spread of superscalar bit: the most recent rename 1, previous 0.
processors. 70Renaming steps. Allocation of a free
5Evolution of superscalar processor. rename register to a destination register
6Specific tasks of superscalar Accessing valid source register value or a
processing. register value that is not yet available
7Parallel decoding {and Dependencies Re-allocation of destination register
check}. What need to be done. Updating a particular rename buffer with a
8Decoding and Pre-decoding. Superscalar computed result De-allocation of a rename
processors tend to use 2 and sometimes buffer that is no longer needed.
even 3 or more pipeline cycles for 71Allocation of a new rename buffer to
decoding and issuing instructions >> destination register (circular buffer:
Pre-decoding: shifts a part of the decode Head and Tail) (before allocation).
task up into loading phase resulting of 72(After allocation) of a destination
pre-decoding the instruction class the register.
type of resources required for the 73Accessing abailable register values.
execution in some processor (e.g. 74Accessing a register value that is not
UltraSparc), branch target addresses yet available. 3 is the index.
calculation as well the results are stored 75Re-allocate of r2 (a destination
by attaching 4-7 bits + shortens the register). 1.
overall cycle time or reduces the number 76Updating the rename buffers with
of cycles needed. computed result of {mul r2, r0, r1}
9The principle of perdecoding. (register 2 with the result 0). 1.
10Number of perdecode bits used. 77Deallocation of the rename buffer no.
11Specific tasks of superscalar 0 (ROB retires instructions) (update tail
processing: Issue. pointer).
127.3 Superscalar instruction issue. How 787.6 Parallel Execution. Executing
and when to send the instruction(s) to several instruction in parallel
EU(s). instructions will generally be finished in
13Issue policies. out-of-program order to finish operation
14Instruction issue policies of of the instruction is accomplished, except
superscalar processors: ---Performance, for writing back the result into the
tread-----? architectural register or memory location
15Issue rate {How many specified, and/or updating the status bits
instructions/cycle}. CISC about 2 RISC: to complete writing back the results to
16Issue policies: Handing Issue retire (ROB) write back the results, and
Blockages. delete the completed instruction from the
17Issue stopped by True dependency. True last ROB entry.
dependency ? (Blocked: need to wait). 797.7 Preserving Sequential Consistency
18Issue order of instructions. of instruction execution //. Multiple EUs
19Aligned vs. unaligned issue. operating in parallel, the overall
20Issue policies: Use of Shelving. instruction execution should >>
21Direct Issue. mimic sequential execution the order in
22The principle of shelving: Indirect which instruction are completed the order
Issue. in which memory is accessed.
23Design space of shelving. 80Sequential consistency models.
24Scope of shelving. 81Consistency relate to instruction
25Layout of shelving buffers. completions or memory access.
26Implementation of shelving buffer. 82Trend and performance.
27Basic variants of shelving buffers. 83Allows the reordering of memory
28Using a combined buffer for shelving, access. it permits load/store reordering
renaming, and reordering. either loads can be performed before
29Number of shelving buffer entries. pending stores, or vice versa a load can
30Number of read and write ports. how be performed before pending stores only IF
many instructions may be written into none of the preceding stores has the same
(input ports) or read out from (output target address as the load it makes
parts) a particular shelving buffer in a Speculative loads or stores feasible When
cycle depend on individual, group, or addresses of pending stores are not yet
central reservation stations. available, speculative loads avoid
31Shelving: Operand fetch policy. delaying memory accesses, perform the load
327.4.4 Operand fetch policies. anywhere. When store addresses have been
33Operand fetch during instruction computed, they are compared against the
issue. Reg. file. addresses of all younger loads. Re-load is
34Operand fetch during instruction needed if any hit is found. it allows
dispatch. Reg. file. cache misses to be hidden if a cache miss,
35Shelving: Instruction dispatch Scheme it allows loads to be performed before the
//. missed load; or it allows stores to be
367.4.5 instruction dispatch scheme. performed before the missed store.
37- Dispatch policy. Selection Rule 84Using Re-Order Buffer (ROB) for
Specifies when instructions are considered Preserving: The order in which instruction
executable e.g. Dataflow principle of are <completed> 1. Instruction are
operation Those instructions whose written into the ROB in strict program
operands are available are executable. order: One new entry is allocated for each
Arbitration Rule Needed when more active instruction 2. Each entry indicates
instructions are eligible for execution the status of the corresponding
than can be disseminated. e.g. choose the instruction issued (i), in execution (x),
‘oldest’ instruction. Dispatch order already finished (f) 3. An instruction is
Determines whether a non-executable allowed to retire only if it has finished
instruction prevents all subsequent and all previous instruction are already
instructions from being dispatched. retired. retiring in strict program order
38Dispatch policy: Dispatch order. only retiring instructions are permitted
39Trend of Dispatch order. to complete, that is, to update the
40-Dispatch rate (instructions/cycle). program state: by writing their result
41Maximum issue rate <= Maximum into the referenced architectural register
dispatch rates >> issue rate reaches or memory.
max more often than dispatch rates. 85Principle of the ROB {Circular
42- Scheme for checking the availability Buffer}.
of operands: The principle of 86Introduction of ROBs in commercial
scoreboarding. superscalar processors. 7.61.
43Schemes for checking the availability 87Use ROB for speculative execution.
of operand. Guess the outcome of a branch and
44Operands fetched during dispatch or execution the path before the condition is
during issue. ready 1. Each entry is extended to include
45Use of multiple buses for updaing a speculative status field indicating
multiple individual reservation strations. whether the corresponding instruction has
46Interal data paths of the powerpc 604. been executed speculatively 2.
42. speculatively executed instruction are not
47-Treatment of an empty reservation allow to retire before the related
station. condition is resolved 3. After the related
487.4.6 Detail Example of Shelving. condition is resolved, if the guess turn
Issuing the following instruction cycle i: out to be right, the instruction can
mul r1, r2, r3 cycle i+1: ad r2, r3, r5 ad retire in order. if the guess is wrong,
r3, r4, r6 format: Rs1, Rs2, Rd. the speculative instructions are marked to
49Example overview. be cancelled. Then, instruction execution
50Cycle i: Issue of the ‘mul’ continue with the correct instructions.
instruction into the reservation station 88Design space of ROBs.
and fetching of the corresponding 89Basic layout of ROBs.
operands. 90ROB implementation details.
51Cycle i+1: Checking for executable 917.8 Preserving the Sequential
instructions and dispatching of the ‘mul’ consistency of exception processing. When
instruction. instructions are executed in parallel,
52Cycle i+1 (2nd phase): Issue of the interrupt request, which are caused by
subsequent two ‘ad’ instructions into the exceptions arising in instruction
reservation station. <execution>, are also generated out
53Cycle i+2: Checking for executable of order. If the requests are acted upon
instruction (mul not yet completed). immediately, the requests are handled in
54Cycle i+3: Updating the FX register different order than in a sequential
file with the result of the ‘mul’ operation processor called imprecise
instruction. interrupts Precise interrupts: handling
55Cycle i+3 (2nd phase): Checking for the interrupts in consistent with the
executable instructions and dispatching state of a sequential processor.
the ‘older’ ’ad’ instruction. 92Sequential consistency of exception
56=Instruction Issue policies:Register processing.
Renaming. 93Use ROB for preserving sequential
57Register Remaining and dependency. order of interrupt requests. Interrupts
three-operand instruction format e.g. Rd, generated in connection with instruction
Rs1, Rs2 False dependency (WAW) mul r2, …, execution can handled at the correct point
… add r2, …, … two different rename buffer in the execution, by accepting interrupt
have to allocated True data dependency requests only when the related instruction
(RAW) mul r2, …, … ad …, r2, … rename to becomes the next to retire.
e.g. mul p12, …, … ad …, p12, …. 947.9 Implementation of superscalar CISC
58Choronology of introduction of processors using superscalar RISC core.
renaming (high complexity, Sparc64 used CISC instructions are first converted into
371K transistors that is more than i386). RISC-like instructions <during
59Static or Dynamic Renaming. decoding>. Simple CISC
60>Design space of register renaming. register-to-register instructions are
61-Scope of register renaming. converted to single RISC operation
62-Layout of rename buffers. (1-to-1) CISC ALU instructions referring
63-Type of rename buffers. to memory are converted to two or more
64Rename buffers hold intermediate RISC operations (1-to-(2-4)) SUB EAX,
results. Each time a Destination register [EDI] converted to e.g. MOV EBX, [EDI] SUB
is referred to, a new rename register is EAX, EBX More complex CISC instructions
allocated to it. Final results are stored are converted to long sequences of RISC
in the Architectural Register file Access operations (1-to-(more than 4)) On average
both rename buffer and architectural one CISC instruction is converted to 1.5-2
register file to find the latest data, if RISC operations.
found in both, the data content in rename 95The peinciple of superscalar CISC
buffer (the intermediate result) is execution using a superscalar RISC core.
chosen. When an instruction completed 96PentiumPro: Decoding/converting CISC
(retired), (ROB) {retire only in strict instructions to RISC operations (are done
program sequence} the correspond rename in program order).
buffer entry is writing into the 97Case Studies: R10000 Core part of the
architectural register file (as a result micro-architecture of the R10000. 67.
modifying the actual program state) the 98Case Studies: PowerPC 620.
correspond rename buffer entry can be 99Case Studies: PentiumPro Core part of
de-allocated. the micro-architecture.
65-Number of rename buffers. 100PentiumPro Long pipeline: Layout of
66-Basic mechanisms used for accessing the FX and load pipelines.
rename buffers. Rename buffers with
TECH Computer Science.ppt
http://900igr.net/kartinka/anglijskij-jazyk/tech-computer-science-136795.html
cсылка на страницу

TECH Computer Science

другие презентации на тему «TECH Computer Science»

«Computer» - and I will be happy to open such a beneficial. I very like a computer. and I want to open computer business. in this business a lot of competitors who are trying to thee . many people buy computers. I love my job. Computer equipment enjoys good success. on the earned money I help the children's kindergartens.

«Youth problems» - Give antogyms: real ly hard ly frank ly actual ly Luck ily honest ly Personal ly. Youth problems: Form adverbs: The right to… Youth groups. Alcohol addiction. Проблемы молодежи. date. Defendant-подсудимый judge-судья plaintiff -истец to arrest-арестовать. Dangerous exciting Hard easy Serious silly Boring false True safe.

«Pointillism» - Complete the sentences. Pointillism. In creation of his first paintings he was influenced by Monet. oil based paints, The scheme of Pointillism. Choose the right variant. «Breakfast». and pencils also can be used. «A still life with a book». «Self-portrait» «Breakfast» «La Tour Eifel» «The Beach Heist».

«The first flight» - Dogs were alive and very happy. In addition to it the dogs must be patient. Epilogue. Then they lived happily in the aviary. Animals got accustomed to wear special uniform. Belka and Strelka made a flight 19 august 1960. Americans began to launch rockets with animals in 1948. Also people taught them to eat from automatic feeding trough.

«Ravers» - Their appearance and behavior promotes a departure from human nature. Performed by Fomyagina Kristina the student of 10(I) form. Fast Food – Volna (video version). Contents. In my opinion subculture the ravers not as bad as it seems. Accessories such as chains, rings - a great success not in use. Dhany – Hit my heart.

«Print advertising» - Types of print advertising. Print advertising rules. Creative business cards. Creative advertising posters in magazines. Advantages of a print advertising. PRINT ADVERTISING. Examples of creative advertising posters in magazines: What is print advertising? They knew how to engage the viewer. Advertising in magazines.

Тексты на английском

46 презентаций о текстах на английском
Урок

Английский язык

29 тем
Картинки