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PALs and PLAs
PALs and PLAs
PALs and PLAs
PALs and PLAs
PALs and PLAs
PALs and PLAs
PALs and PLAs
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Steering Logic: Switches
Steering Logic: Switches
Steering Logic
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Multiplexers/Selectors
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OE 0 1 1
OE 0 1 1
Tri-state and Open Collector
Tri-state and Open Collector
Tri-state and Open Collector
Tri-state and Open Collector
Tri-state and Open Collector
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Read-Only Memories
Read-Only Memories
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Combinational Logic Word Problems
Combinational Logic Word Problems
Combinational Logic Word Problems
Combinational Logic Word Problems
Combinational Logic Word Problems
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Combinational Logic Word Problems
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Combinational Logic Word Problems
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Chapter 4: Programmable and Steering Logic Contemporary Logic Design Randy H. Katz University of California, Berkeley June 1993

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1Chapter # 4: Programmable and Steering 45Multiplexers/Decoders. 5:32 Decoder.
Logic Contemporary Logic Design Randy H. 46OE 0 1 1. A X 0 1. F Z 0 1. Tri-State
Katz University of California, Berkeley and Open-Collector. The Third State. Logic
June 1993. States: "0", "1" Don't
2Chapter Overview. • PALs and PLAs • Care/Don't Know State: "X" (must
Non-Gate Logic Switch Logic be some value in real circuit!) Third
Multiplexers/Selecters and Decoders State: "Z" — high impedance —
Tri-State Gates/Open Collector Gates ROM • infinite resistance, no connection.
Combinational Logic Design Problems Seven Tri-state gates: output values are
Segment Display Decoder Process Line "0", "1", and
Controller Logical Function Unit Barrel "Z" additional input: output
Shifter. enable (OE). When OE is high, this gate is
3PALs and PLAs. Pre-fabricated building a non-inverting "buffer" When OE
block of many AND/OR gates (or NOR, NAND) is low, it is as though the gate was
"Personalized" by making or disconnected from the output! This allows
breaking connections among the gates. more than one gate to be connected to the
Programmable Array Block Diagram for Sum same output wire, as long as only one has
of Products Form. its output enabled at the same time.
4PALs and PLAs. Key to Success: Shared Non-inverting buffer's timing waveform.
Product Terms. Equations. F0 = A + B' C' "Z" "Z"
F1 = A C' + A B F2 = B' C' + A B F3 = B' C 47Tri-state and Open Collector. Using
+ A. Example: Input Side: 1 = asserted in tri-state gates to implement an economical
term 0 = negated in term - = does not multiplexer: When SelectInput is asserted
participate. Personality Matrix. Output high Input1 is connected to F When
Side: 1 = term connected to output 0 = no SelectInput is driven low Input0 is
connection to output. connected to F This is essentially a 2:1
5PALs and PLAs. Example Continued. All Mux.
possible connections are available before 48Tri-state and Open Collector.
programming. Alternative Tri-state Fragment. Active low
6PALs and PLAs. Example Continued. tri-state enables plus inverting tri-state
Unwanted connections are "blown" buffers. Switch Level Implementation of
Note: some array structures work by making tri-state gate.
connections rather than breaking them. 49Tri-State and Open Collector. 4:1
7PALs and PLAs. Alternative Multiplexer, Revisited. Decoder + 4
representation for high fan-in structures. tri-state Gates.
Short-hand notation so we don't have to 50Tri-State and Open Collector. Open
draw all the wires! Notation for Collector. another way to connect multiple
implementing F0 = A B + A' B' F1 = C D' + gates to the same output wire gate only
C' D. has the ability to pull its output low; it
8PALs and PLAs. Design Example. cannot actively drive the wire high this
Multiple functions of A, B, C. F1 = A B C is done by pulling the wire up to a logic
F2 = A + B + C F3 = A B C F4 = A + B + C 1 voltage through a resistor. OC NAND
F5 = A xor B xor C F6 = A xnor B xnor C. gates. Wired AND: If A and B are
9PALs and PLAs. What is difference "1", output is actively pulled
between Programmable Array Logic (PAL) and low if C and D are "1", output
Programmable Logic Array (PLA)? PAL is actively pulled low if one gate is low,
concept — implemented by Monolithic the other high, then low wins if both
Memories constrained topology of the OR gates are "1", the output
Array. A given column of the OR array has floats, pulled high by resistor Hence, the
access to only a subset of the possible two NAND functions are AND'd together!
product terms. PLA concept — generalized 51Tri-State and Open Collector. 4:1
topologies in AND and OR planes. Multiplexer. Decoder + 4 Open Collector
10PALs and PLAs. Design Example: BCD to Gates.
Gray Code Converter. Truth Table. K-maps. 52Read-Only Memories. ROM: Two
Minimized Functions: W = A + B D + B C X = dimensional array of 1's and 0's. Row is
B C' Y = B + C Z = A'B'C'D + B C D + A D' called a "word"; index is called
+ B' C D'. an "address" Width of row is
11PALs and PLAs. Programmed PAL: 4 called bit-width or wordsize Address is
product terms per each OR gate. input, selected word is output. Internal
12PALs and PLAs. Code Converter Discrete Organization.
Gate Implementation. 4 SSI Packages vs. 1 53Read-Only Memories. Example:
PLA/PAL Package! Combination Logic Implementation. F0 = A'
13PALs and PLAs. Another Example: B' C + A B' C' + A B' C F1 = A' B' C + A'
Magnitude Comparator. B C' + A B C F2 = A' B' C' + A' B' C + A
14Non-Gate Logic. Introduction. B' C' F3 = A' B C + A B' C' + A B C'. by.
AND-OR-Invert PAL/PLA. Generalized 54Read-Only Memories. Not unlike a PLA
Building Blocks Beyond Simple Gates. Kinds structure with a fully decoded AND array!
of "Non-gate logic": • switching ROM vs. PLA: ROM approach advantageous
circuits built from CMOS transmission when (1) design time is short (no need to
gates • multiplexer/selecter functions • minimize output functions) (2) most input
decoders • tri-state and open collector combinations are needed (e.g., code
gates • read-only memories. converters) (3) little sharing of product
15Steering Logic: Switches. Voltage terms among output functions ROM problem:
Controlled Switches. n-type Si. p-type Si. size doubles for each additional input,
"n-Channel MOS" Metal Gate, can't use don't cares PLA approach
Oxide, Silicon Sandwich Diffusion regions: advantangeous when (1) design tool like
negatively charged ions driven into Si espresso is available (2) there are
surface Si Bulk: positively charged ions relatively few unique minterm combinations
By "pulling" electrons to the (3) many minterms are shared among the
surface, a conducting channel is formed. output functions PAL problem: constrained
16Steering Logic. Voltage Controlled fan-ins on OR planes.
Switches. Logic 1 on gate, Source and 55Read-Only Memories. 2764 EPROM 8K x 8.
Drain connected. Logic 0 on gate, Source 16K x 16 Subsystem.
and Drain connected. 56Combinational Logic Word Problems.
17Steering Logic. Logic Gates from General Design Procedure. 1. Understand
Switches. NOR Gate. NAND Gate. Inverter. the Problem what is the circuit supposed
Pull-up network constructed from pMOS to do? write down inputs (data, control)
transistors Pull-down network constructed and outputs draw block diagram or other
from nMOS transistors. picture 2. Formulate the Problem in terms
18Steering Logic. Inverter Operation. of a truth table or other suitable design
Input is 1 Pull-up does not conduct representation truth table or waveform
Pull-down conducts Output connected to diagram 3. Choose Implementation Target
GND. Input is 0 Pull-up conducts Pull-down ROM, PAL, PLA, Mux, Decoder + OR, Discrete
does not conduct Output connected to VDD. Gates 4. Follow Implementation Procedure
19Steering Logic. NAND Gate Operation. A K-maps, espresso, misII.
= 0, B = 1 Pull-up network has path to VDD 57Combinational Logic Word Problems.
Pull-down network path broken Output node Process Line Control Problem. Statement of
connected to VDD. A = 1, B = 1 Pull-up the Problem. Rods of varying length
network does not conduct Pull-down network (+/-10%) travel on conveyor belt
conducts Output node connected to GND. Mechanical arm pushes rods within spec
20Steering Logic. NOR Gate Operation. A (+/-5%) to one side Second arm pushes rods
= 0, B = 0 Pull-up network conducts too long to other side Rods too short stay
Pull-down network broken Output node at on belt 3 light barriers (light source +
VDD. A = 1, B = 0 Pull-up network broken photocell) as sensors Design combinational
Pull-down network conducts Output node at logic to activate the arms. Understanding
GND. the Problem. Inputs are three sensors,
21Steering Logic. CMOS Transmission outputs are two arm control signals Assume
Gate. nMOS transistors good at passing 0's sensor reads "1" when tripped,
but bad at passing 1's pMOS transistors "0" otherwise Call sensors A, B,
good at passing 1's but bad at passing 0's C Draw a picture!
perfect "transmission" gate 58Combinational Logic Word Problems.
places these in parallel: Transmission or Process Control Problem. Where to place
"Butterfly" Gate. Switches. the light sensors A, B, and C to
Transistors. distinguish among the three cases? Assume
22Steering Logic. Selection that A detects the leading edge of the rod
Function/Demultiplexer Function with on the conveyor.
Transmission Gates. Selector: Choose I0 if 59Combinational Logic Word Problems.
S = 0 Choose I1 if S = 1. Demultiplexer: I Process Control Problem. A to B distance
to Z0 if S = 0 I to Z1 if S = 1. place apart at specification - 5% A to C
23Steering Logic. Use of distance placed apart at specification
Multiplexer/Demultiplexer in Digital +5%.
Systems. So far, we've only seen 60Combinational Logic Word Problems.
point-to-point connections among gates Process Control Problem. Truth table and
Mux/Demux used to implement multiple logic implementation now straightforward.
source/multiple destination interconnect. "too long" = A B C (all three
24Steering Logic. Well-formed Switching sensors tripped) "in spec" = A B
Networks. Problem with the Demux C' (first two sensors tripped).
implementation: multiple outputs, but only 61Combinational Logic Word Problems. BCD
one connected to the input! The fix: to 7 Segment Display Controller.
additional logic to drive every output to Understanding the problem: input is a 4
a known value Never allow outputs to bit bcd digit output is the control
"float" signals for the display 4 inputs A, B, C,
25Steering Logic. Complex Steering Logic D 7 outputs C0 — C6. Block Diagram.
Example. N Input Tally Circuit: count # of 62Combinational Logic Word Problems. BCD
1's in the inputs. Conventional Logic for to 7 Segment Display Controller. Formulate
1 Input Tally Function. Switch Logic the problem in terms of a truth table.
Implementation of Tally Function. Choose implementation target: if ROM, we
26Steering Logic. Complex Steering Logic are done don't cares imply PAL/PLA may be
Example. Operation of the 1 Input Tally attractive. Follow implementation
Circuit. Input is 0, straight through procedure: hand reduced K-maps vs.
switches enabled. espresso.
27Steering Logic. Complex Steering Logic 63Combinational Logic Word Problems. BCD
Example. Operation of 1 input Tally to 7 Segment Display Controller. C0 = A +
Circuit. Input = 1, diagonal switches B D + C + B' D' C1 = A + C' D' + C D + B'
enabled. C2 = A + B + C' + D. C3 = B' D' + C D' + B
28Steering Logic. Complex Steering Logic C' D + B' C C4 = B' D' + C D C5 = A + C'
Example. Extension to the 2-input case. D' + B D' + B C' C6 = A + C D' + B C' + B'
Conventional logic implementation. C. 14 Unique Product Terms.
29Steering Logic. Complex Steering Logic 64Combinational Logic Word Problems. BCD
Example. Switch Logic Implementation: to 7 Segment Display Controller. 16H8PAL
2-input Tally Circuit. Cascade the 1-input Can Implement the function.
implementation! 65Combinational Logic Word Problems. BCD
30Steering Logic. Complex Steering Logic to 7 Segment Display Controller. 14H8PAL
Example. Operation of 2-input Cannot Implement the function.
implementation. 66Combinational Logic Word Problems. BCD
31Multiplexers/Selectors. Use of to7 Segment Display Controller. C0 = B C'
Multiplexers/Selectors. Multi-point D + C D + B' D' + B C D' + A C1 = B' D +
connections. Multiple input sources. C' D' + C D + B' D' C2 = B' D + B C' D +
Multiple output destinations. C' D' + C D + B C D' C3 = B C' D + B' D +
32Multiplexers/Selectors. General B' D' + B C D' C4 = B' D' + B C D' C5 = B
Concept. n. 2 data inputs, n control C' D + C' D' + A + B C D' C6 = B' C + B C'
inputs, 1 output used to connect 2 points + B C D' + A 9 Unique Product Terms!
to a single point control signal pattern espresso output. 63 Literals, 20 Gates.
form binary index of input connected to espresso input. .i 4 .o 7 .ilb a b c d .ob
output. n. Z = A' I + A I. 0. 1. c0 c1 c2 c3 c4 c5 c6 .p 16 0000 1111110
Functional form. Logical form. Two 0001 0110000 0010 1101101 0011 1111001
alternative forms for a 2:1 Mux Truth 0100 0110011 0101 1011011 0110 1011111
Table. 0111 1110000 1000 1111111 1001 1110011
33Multiplexers/Selectors. Z = A' I + A 1010 ------- 1011 ------- 1100 -------
I. 0. 1. Z = A' B' I0 + A' B I1 + A B' I2 1101 ------- 1110 ------- 1111 ------- .e.
+ A B I3. Z = A' B' C' I0 + A' B' C I1 + .i 4 .o 7 .ilb a b c d .ob c0 c1 c2 c3 c4
A' B C' I2 + A' B C I3 + A B' C' I4 + A B' c5 c6 .p 9 -10- 0000001 -01- 0001001 -0-1
C I5 + A B C' I6 + A B C I7. n. 2 -1. In 0110000 -101 1011010 --00 0110010 --11
general, Z = ? m I. k=0. k. k. n. in 1110000 -0-0 1101100 1--- 1000011 -110
minterm shorthand form for a 2 :1 Mux. 1011111 .e.
34Multiplexers/Selectors. Alternative 67Combinational Logic Word Problems. BCD
Implementations. Transmission Gate to 7 Segment Display Controller. PLA
Implementation of 4:1 Mux. Gate Level Implementation.
Implementation of 4:1 Mux. twenty 68Combinational Logic Word Problems. BCD
transistors. thirty six transistors. to7 Segment Display Controller. Multilevel
35Multiplexer/Selector. Large Implementation. X = C' + D' Y = B' C' C0 =
multiplexers can be implemented by C3 + A' B X' + A D Y C1 = Y + A' C5' + C'
cascaded smaller ones. Control signals B D' C6 C2 = C5 + A' B' D + A' C D C3 = C4 +
and C simultaneously choose one of I0-I3 B D C5 + A' B' X' C4 = D' Y + A' C D' C5 =
and I4-I7 Control signal A chooses which C' C4 + A Y + A' B X C6 = A C4 + C C5 +
of the upper or lower MUX's output to gate C4' C5 + A' B' C. 52 literals 33 gates
to Z. Alternative 8:1 Mux Implementation. Ineffective use of don't cares.
36Multiplexer/Selector. 69Combinational Logic Word Problems.
Multiplexers/selectors as a general Logical Function Unit. Statement of the
purpose logic block. n-1. 2 :1 multiplexer Problem: 3 control inputs: C0, C1, C2 2
can implement any function of n variables data inputs: A, B 1 output: F.
n-1 control variables; remaining variable 70Combinational Logic Word Problems.
is a data input to the mux. Example: Logical Function Unit. Formulate as a
F(A,B,C) = m0 + m2 + m6 + m7. = A' B' C' + truth table Choose implementation
A' B C' + A B C' + A B C = A' B' (C') + A' technology 5-variable K-map espresso
B (C') + A B' (0) + A B (1). "Lookup multiplexor implementation. 4 TTL
Table" packages: 4 x 2-input NAND 4 x 2-input NOR
37Multiplexer/Selector. Generalization. 2 x 2-input XOR 8:1 MUX.
Four possible configurations of the truth 71Combinational Logic Word Problems.
table rows. n-1 Mux control variables. Logical Function Unit. Follow
single Mux data variable. Can be expressed implementation procedure. F = C2' A' B' +
as a function of In, 0, 1. Example: C0' A B' + C0' A' B + C1' A B. 5 gates, 5
G(A,B,C,D) can be implemented by an 8:1 inverters Also four packages: 4 x 3-input
MUX: K-map Choose A,B,C as control NAND 1 x 4-input NAND Alternative: 32 x
variables. Multiplexer Implementation. TTL 1-bit ROM single package.
package efficient May be gate inefficient. 72Combinational Logic Word Problems.
38Decoders/Demultiplexers. n. Decoder: 8-Input Barrel Shifter. Specification:
single data input, n control inputs, 2 Inputs: D7, D6, …, D0 Outputs: O7, O6, …,
outputs control inputs (called select S) O0 Control: S2, S1, S0. shift input the
represent Binary index of output to which specified number of positions to the
the input is connected data input usually right. Understand the problem: D7 D6 D5 D4
called "enable" (G). 1:2 D3 D2 D1 D0. O7 O6 O5 O4 O3 O2 O1 O0. D7
Decoder: 3:8 Decoder: O0 = G • S0 • S1 • D6 D5 D4 D3 D2 D1 D0. O7 O6 O5 O4 O3 O2 O1
S2 O1 = G • S0 • S1 • S2 O2 = G • S0 • S1 O0. D7 D6 D5 D4 D3 D2 D1 D0. O7 O6 O5 O4
• S2 O3 = G • S0 • S1 • S2 O4 = G • S0 • O3 O2 O1 O0. . . . . . . . . . S2, S1, S0
S1 • S2 O5 = G • S0 • S1 • S2 O6 = G • S0 = 0 0 1. S2, S1, S0 = 0 0 0. S2, S1, S0 =
• S1 • S2 O7 = G • S0 • S1 • S2. O0 = G • 0 1 0.
S; O1 = G • S. 2:4 Decoder: O0 = G • S0 • 73Combinational Logic Word Problems.
S1 O1 = G • S0 • S1 O2 = G • S0 • S1 O3 = 8-Input Barrel Shifter. Function Table.
G • S0 • S1. Boolean equations. O7 = S2' S1' S0' D7 +
39Decoders/Demultiplexers. Alternative S2' S1' S0 D6 + … + S2 S1 S0 D0 O6 = S2'
Implementations. 1:2 Decoder, Active Low S1' S0' D6 + S2' S1' S0 D5 + … + S2 S1 S0
Enable. 1:2 Decoder, Active High Enable. D7 O5 = S2' S1' S0' D5 + S2' S1' S0 D4 + …
2:4 Decoder, Active Low Enable. 2:4 + S2 S1 S0 D6 O4 = S2' S1' S0' D4 + S2'
Decoder, Active High Enable. S1' S0 D3 + … + S2 S1 S0 D5 O3 = S2' S1'
40Decoders/Demultiplexers. Switch Logic S0' D3 + S2' S1' S0 D2 + … + S2 S1 S0 D4
Implementations. Naive, Incorrect O2 = S2' S1' S0' D2 + S2' S1' S0 D1 + … +
Implementation All outputs not driven at S2 S1 S0 D3 O1 = S2' S1' S0' D1 + S2' S1'
all times. Correct 1:2 Decoder S0 D0 + … + S2 S1 S0 D2 O0 = S2' S1' S0'
Implementation. D0 + S2' S1' S0 D7 + … + S2 S1 S0 D1.
41Decoders/Demultiplexers. Switch 74Combinational Logic Word Problems.
Implementation of 2:4 Decoder. Operation 8-Input Barrel Shifter. Straightforward
of 2:4 Decoder. S0 = 0, S1 = 0 one gate logic implementation OR 8 by 8:1
straight thru path three diagonal paths. multiplexer (wiring mess!) OR Switch
42Decoder/Demultiplexer. Decoder as a logic. Crosspoint switches. Fully Wired
Logic Building Block. Decoder Generates crosspoint switch.
Appropriate Minterm based on Control 75Chapter Review. • Non-Simple Gate
Signals. Example Function: F1 = A' B C' D Logic Building Blocks: • Combinational
+ A' B' C D + A B C D F2 = A B C' D' + A B Word Problems: PALs/PLAs
C F3 = (A' + B' + C' + D'). Multiplexers/Selecters Decoders ROMs
43Decoder/Demultiplexer. Decoder as a Tri-state, Open Collector. Understand the
Logic Building Block. If active low Problem Formulate in terms of a Truth
enable, then use NAND gates! Table Choose implementation technology
44Multiplexers/Decoders. Alternative Implement by following the design
Implementations of 32:1 Mux. Multiplexer + procedure.
Decoder. Multiplexer Only.
Chapter 4: Programmable and Steering Logic Contemporary Logic Design Randy H. Katz University of California, Berkeley June 1993.ppt
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Chapter 4: Programmable and Steering Logic Contemporary Logic Design Randy H. Katz University of California, Berkeley June 1993

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