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State Machine Design
State Machine Design
Examples of State Machines
Examples of State Machines
Examples of State Machines
Examples of State Machines
Examples of State Machines
Examples of State Machines
State Graphs
State Graphs
State Variables
State Variables
State Graphs to State Transition Tables
State Graphs to State Transition Tables
Step 6: Circuit Design – AOI Simplified
Step 6: Circuit Design – AOI Simplified
Step 8: Circuit Design – Simplified Further XOR
Step 8: Circuit Design – Simplified Further XOR
State Machine Block Diagram / Schematic
State Machine Block Diagram / Schematic
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State Machine Design

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1State Machine Design. Digital 16State Graphs to State Transition
Electronics. © 2014 Project Lead The Way, Tables. 16.
Inc. 17State Transition Tables. State
2State Machine Design. This Transition Tables are then created from
presentation will Define a state machine the State Graph. They describe the Present
and Illustrate the block diagram for a State (inputs) and the Next State
state machine. Provide several examples of (outputs) associated with each state
everyday items that are controlled by (S0-S3). 17.
state machines. Describe the steps in the 18State Transition Tables. Notice that
state machine design process. Provide an each state occupies 2 lines on the State
example of a state machine design. 2. Transition Table. That is because (in this
3State Machine. A synchronous example) each transition is triggered by
sequential circuit, consisting of a only one of 4 possible inputs at any time.
sequential logic section and a For: Input that causes transition: S0 OS =
combinational logic section, whose outputs 0 ;OS = 1 S1 OL = 0 ;OS = 1 S2 CS = 0 ;CS
and internal flip-flops progress through a =1 S3 CL = 0 ;CL = 1. 18.
predictable sequence of states in response 19State Transition Tables. In a state
to a clock and other input signals.? machine, the Next State is actually the
Memory Flip-Flops. Input Combo Logic. output from the Memory flip-flops (Qa*
Output Combo Logic. Output(s). Input(s). Qb*) when an input is changed. Qa* = Da
Clock. 3. for the next state on one flip-flop and
4Parts of a State Machine. Input Qb* = Db for the next state on the other
Combinational Logic Memory Output flip-flop. 19.
Combinational Logic. Memory Flip-Flops. 20State Transition Tables. The outputs
Input Combo Logic. Output Combo Logic. from the Memory flip-flops are linked to
Output(s). Input(s). Clock. 4. the Input Combinational Logic. That way a
5Input Combinational Logic. What should transition is made on the next clock
happen next based on the buttons, signal to the next state. Qa* = Da for the
switches, and other inputs? Memory next state on one flip-flop and Qb* = Db
Flip-Flops. Input Combo Logic. Output for the next state on the other flip-flop.
Combo Logic. Output(s). Input(s). Clock. Memory Flip-Flops. Input Combo Logic.
5. Output Combo Logic. Output(s). Input(s).
6Memory. Flip-Flops determine the Clock. 20.
number of states in the design and trigger 21Design Equations. From the State
the state transitions based on the inputs. Transition Table you can now determine the
Memory Flip-Flops. Input Combo Logic. un-simplified expressions for the: Input
Output Combo Logic. Output(s). Input(s). Combinational Logic Da=Qa* Db=Qb* Output
Clock. 6. Combinational Logic This example has (4)
7Output Combinational Logic. What outputs MO – Motor Open Signal MC – Motor
should motors, indicators, and other Close Signal GO – Gate Open Indicator GC –
outputs do once the flip-flops have caused Gate Closed Indicator. 21.
the transition to a new state? Memory 22State Machine Design Example. Design a
Flip-Flops. Input Combo Logic. Output state machine that will count out the last
Combo Logic. Output(s). Input(s). Clock. four digits of a phone number ONLY when an
7. Enable pushbutton is pressed. The output
8Examples of State Machines. Many should hold the last number until the
everyday devices are controlled by state Enable button is pressed again. (Example
machines. Traffic Lights Garage Door 585-476-4691) Whenever the Enable is a
Numeric Keypads Vending Machines. 8. logic (1), the outputs will continuously
9State Machine Design. Create a State cycle through the four values 4,6,9,1.
Graph Determine the number of States and Whenever the Enable is a logic (0), the
label Determine the number of State outputs will hold at their current values.
Variables and label (How many flip-flops For this design any form of combinational
needed?) Label Outputs and Encode Outputs logic may be used, but the sequential
to States Create State Transition Table logic must be limited to D flip-flops. 22.
from the State Graph Write and Simplify 23Step 1: Create State Graph (# of
Design Equations from the State Transition States?). EN = 0. EN = 1. EN = 1. EN = 0.
Table Design Circuit. 9. EN = 0. EN = 1. EN = 1. EN = 0. 23.
10State Graphs. A state graph shows the 24Step 2: Determine # of State Variables
sequence of states that the state machine and Assign. EN = 0. EN = 1. EN = 1. EN =
will transition to on each clock 0. EN = 0. EN = 1. EN = 1. EN = 0. 24.
transition. This is an example of a state 25Step 3: Encode Outputs to States (#
graph with four states (S0-S3). 10. Displayed?). EN = 0. EN = 1. EN = 1. EN =
11State Graphs. Each state “bubble” is 0. EN = 0. EN = 1. EN = 1. EN = 0. 25.
labeled (S0,S1,S2,S3). These labels are 0100 C3=0 C2=1 C1=0 C0=0. 1001 C3=1 C2=0
arbitrary. Each transition arc is labeled C1=0 C0=1. 0001 C3=0 C2=0 C1=0 C0=1. 0110
with the values of the input variables C3=0 C2=1 C1=1 C0=0.
that make the transition occur. 11. 26Step 4: Create State Transition Table.
12Anatomy of a State Graph. Transition State. State. State. State. State. State.
Arc (For Input X=0) Hold State. Input Inputs. Inputs. Inputs. Outputs. Outputs.
Variable (X). State (S0). State “Bubble”. Outputs. Outputs. Outputs. Outputs.
Transition Arc (For Input X=1) Next State. Outputs. Outputs. Qa. Qb. EN. Qa*. Qb*.
State Variables (Qa & Qb). Next State Da. Db. C3. C2. C1. C0. S0. 0. 0. 0. S0.
“Bubble”. Output Variables (Y & Z). 0. 0. 0. 0. 0. 1. 0. 0. S0. 0. 0. 1. S1.
12. 0. 1. 0. 1. 0. 1. 0. 0. S1. 0. 1. 0. S1.
13State Variables. The state variables 0. 1. 0. 1. 0. 1. 1. 0. S1. 0. 1. 1. S2.
are actually the outputs of the memory 1. 0. 1. 0. 0. 1. 1. 0. S2. 1. 0. 0. S2.
flip-flops. For that reason they are 1. 0. 1. 0. 1. 0. 0. 1. S2. 1. 0. 1. S3.
typically labeled Qa, Qb, etc. S0. This 1. 1. 1. 1. 1. 0. 0. 1. S3. 1. 1. 0. S3.
four state example would require (2) 1. 1. 1. 1. 0. 0. 0. 1. S3. 1. 1. 1. S0.
flip-flip (Qa and Qb) to clock through 0. 0. 0. 0. 0. 0. 0. 1. See Slide Notes
four states (S0-S3). 1st State (SO) Qa Qb for a detailed description. Present State.
= 0 0 2nd State (S1) Qa Qb = 0 1 3rd State Present State. Input. Next State. Next
(S2) Qa Qb = 1 0 4th State (S3) Qa Qb = 1 State. F/F Inputs. F/F Inputs. Encoded
1. Qa Qb 0 0. 13. Outputs. Encoded Outputs. Encoded Outputs.
14State Variables. If a 5th state was Encoded Outputs. 26.
needed: Can you guess how many flip-flops 27Step 5: Write and Simplify Design
and state variables you would need? (It is Equations. 27.
not possible to have exactly 5 states) How 28Step 6: Circuit Design – AOI
many states would go un-used? 1st State Simplified. Can you think of a better way
(SO) Qa Qb = 0 0 2nd State (S1) Qa Qb = 0 to impliment the logic for Db ? 28.
1 3rd State (S2) Qa Qb = 1 1 4th State 29Step 7: Circuit Design – Simplified
(S3) Qa Qb = 1 1 5th Sate (S4) ??????? = Further? 29.
????? 14. 30Step 8: Circuit Design – Simplified
15Output Variables. Each state “bubble” Further XOR. 30.
is assigned output variables. This example 31State Machine Block Diagram /
has 4 output variables based on what state Schematic. 31.
it is in. 15.
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State Machine Design

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