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CS136, Advanced Architecture
CS136, Advanced Architecture
Outline
Outline
Digression: Virtual Time
Digression: Virtual Time
Speculation to Achieve Greater ILP
Speculation to Achieve Greater ILP
Speculation to Achieve Greater ILP
Speculation to Achieve Greater ILP
Adding Speculation to Tomasulo
Adding Speculation to Tomasulo
Reorder Buffer (ROB)
Reorder Buffer (ROB)
Reorder Buffer Entry
Reorder Buffer Entry
Reorder Buffer operation
Reorder Buffer operation
4 Steps of Speculative Tomasulo Algorithm
4 Steps of Speculative Tomasulo Algorithm
Tomasulo With Reorder buffer:
Tomasulo With Reorder buffer:
Tomasulo With Reorder buffer:
Tomasulo With Reorder buffer:
Tomasulo With Reorder buffer:
Tomasulo With Reorder buffer:
Tomasulo With Reorder buffer:
Tomasulo With Reorder buffer:
Tomasulo With Reorder buffer:
Tomasulo With Reorder buffer:
Tomasulo With Reorder buffer:
Tomasulo With Reorder buffer:
Tomasulo With Reorder buffer:
Tomasulo With Reorder buffer:
Tomasulo With Reorder buffer:
Tomasulo With Reorder buffer:
Avoiding Memory Hazards
Avoiding Memory Hazards
Exceptions and Interrupts
Exceptions and Interrupts
Getting CPI Below 1
Getting CPI Below 1
VLIW: Very Long Instruction Word
VLIW: Very Long Instruction Word
Recall: Unrolled Loop that Minimizes Scalar Stalls
Recall: Unrolled Loop that Minimizes Scalar Stalls
Loop Unrolling in VLIW
Loop Unrolling in VLIW
Problems with 1st-Generation VLIW
Problems with 1st-Generation VLIW
Intel/HP IA-64 Explicitly Parallel Instruction Computer (EPIC)
Intel/HP IA-64 Explicitly Parallel Instruction Computer (EPIC)
Increasing Instruction-Fetch Bandwidth
Increasing Instruction-Fetch Bandwidth
IF BW: Return Address Predictor
IF BW: Return Address Predictor
More Instruction-Fetch Bandwidth
More Instruction-Fetch Bandwidth
Speculation: Register Renaming vs
Speculation: Register Renaming vs
Value Prediction
Value Prediction
(Mis) Speculation on Pentium 4
(Mis) Speculation on Pentium 4
Perspective
Perspective
In Conclusion
In Conclusion

: CS136, Advanced Architecture. : . : CS136, Advanced Architecture.ppt. zip-: 613 .

CS136, Advanced Architecture

CS136, Advanced Architecture.ppt
1 CS136, Advanced Architecture

CS136, Advanced Architecture

Speculation

2 Outline

Outline

Speculation Speculative Tomasulo Example Memory Aliases Exceptions VLIW Increasing instruction bandwidth Register Renaming vs. Reorder Buffer Value Prediction

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3 Digression: Virtual Time

Digression: Virtual Time

David R. Jefferson, TOPLAS 85: Virtual Time Introduced Time Warp operating system Designed for parallel discrete-event simulation Old way: if message might come from other CPU, wait Meant that your CPU was idle and useless Daves idea: assume that the incoming message wouldnt happen or didnt matter Continue computing happily If correct, your time was used productively If not, you would have been idle anyway; roll back and repeat the computation with correct information This idea of speculation is applicable in many places, including hardware

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4 Speculation to Achieve Greater ILP

Speculation to Achieve Greater ILP

Greater ILP: Overcome control dependence by hardware speculating on outcome of branches and executing program as if guesses were correct Speculation ? fetch, issue, and execute instructions as if branch predictions were always correct Dynamic scheduling ? only fetches and issues instructions Essentially a data flow execution model: Operations execute as soon as their operands are available

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5 Speculation to Achieve Greater ILP

Speculation to Achieve Greater ILP

3 components of HW-based speculation: Dynamic branch prediction to choose which instructions to execute Speculation to allow execution of instructions before control dependences are resolved + Ability to undo effects of incorrectly speculated sequence Dynamic scheduling to deal with scheduling of different combinations of basic blocks

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6 Adding Speculation to Tomasulo

Adding Speculation to Tomasulo

Must separate execution from allowing instruction to finish or commit This additional step is called instruction commit When an instruction is no longer speculative, allow it to update register file or memory Requires additional set of buffers to hold results of instructions that have finished execution but have not committed This reorder buffer (ROB) is also used to pass results among instructions that may be speculated

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7 Reorder Buffer (ROB)

Reorder Buffer (ROB)

In Tomasulos algorithm, once an instruction writes its result, any subsequently issued instructions will find result in register file With speculation, register file is not updated until instruction commits (I.e. we know definitively that the instruction should execute) Thus, ROB supplies operands in interval between completion of instruction execution and instruction commit ROB is a source of operands for instructions, just as reservation stations (RS) provide operands in Tomasulos algorithm ROB extends architectured registers just like RSes do

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8 Reorder Buffer Entry

Reorder Buffer Entry

Each entry in the ROB contains four fields: Instruction type Branch (has no destination result), store (has memory-address destination), or register operation (ALU operation or load, which has register destinations) Destination Register number (for loads and ALU operations) or memory address (for stores) where instruction result should be written Value Value of instruction result until instruction commits Ready Indicates that instruction has completed execution and result is ready

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9 Reorder Buffer operation

Reorder Buffer operation

Holds instructions in FIFO order, exactly as issued When instructions complete, results placed into ROB Supplies operands to other instruction between execution complete & commit ? more registers like RS Tag results with ROB buffer number instead of reservation station Instructions commit ?values at head of ROB placed in registers As a result, easy to undo speculated instructions on mispredicted branches or on exceptions

Commit path

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10 4 Steps of Speculative Tomasulo Algorithm

4 Steps of Speculative Tomasulo Algorithm

1. Issueget instruction from FP Op Queue If reservation station and reorder buffer slot free, issue instr & send operands & reorder buffer no. for destination (this stage sometimes called dispatch) 2. Executionoperate on operands (EX) When both operands ready then execute; if not ready, watch CDB for result; when both in reservation station, execute; checks RAW (sometimes called issue) 3. Write resultfinish execution (WB) Write on Common Data Bus to all awaiting FUs & reorder buffer; mark reservation station available. 4. Commitupdate register with reorder result When instr. at head of reorder buffer & result present, update register with result (or store to memory) and remove instr from reorder buffer. Mispredicted branch flushes reorder buffer (sometimes called graduation)

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11 Tomasulo With Reorder buffer:

Tomasulo With Reorder buffer:

Reorder Buffer

Registers

Done?

FP Op Queue

Newest

Oldest

F0

LD F0,10(R2)

N

To Memory

Dest

from Memory

Dest

Dest

Reservation Stations

FP adders

FP multipliers

ROB7 ROB6 ROB5 ROB4 ROB3 ROB2 ROB1

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12 Tomasulo With Reorder buffer:

Tomasulo With Reorder buffer:

Reorder Buffer

Registers

Done?

FP Op Queue

Newest

Oldest

To Memory

Dest

from Memory

Dest

2 ADDD R(F4),ROB1

Dest

Reservation Stations

FP adders

FP multipliers

ROB7 ROB6 ROB5 ROB4 ROB3 ROB2 ROB1

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13 Tomasulo With Reorder buffer:

Tomasulo With Reorder buffer:

Reorder Buffer

Registers

Done?

FP Op Queue

Newest

Oldest

To Memory

Dest

from Memory

Dest

2 ADDD R(F4),ROB1

Dest

Reservation Stations

FP adders

FP multipliers

ROB7 ROB6 ROB5 ROB4 ROB3 ROB2 ROB1

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14 Tomasulo With Reorder buffer:

Tomasulo With Reorder buffer:

Reorder Buffer

Registers

Done?

FP Op Queue

Newest

Oldest

To Memory

Dest

from Memory

Dest

2 ADDD R(F4),ROB1

6 ADDD ROB5, R(F6)

Dest

Reservation Stations

1 10+R2

5 0+R3

FP adders

FP multipliers

ROB7 ROB6 ROB5 ROB4 ROB3 ROB2 ROB1

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15 Tomasulo With Reorder buffer:

Tomasulo With Reorder buffer:

Reorder Buffer

Registers

Done?

FP Op Queue

Newest

Oldest

To Memory

Dest

from Memory

Dest

2 ADDD R(F4),ROB1

6 ADDD ROB5, R(F6)

Dest

Reservation Stations

1 10+R2

5 0+R3

FP adders

FP multipliers

ROB7 ROB6 ROB5 ROB4 ROB3 ROB2 ROB1

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16 Tomasulo With Reorder buffer:

Tomasulo With Reorder buffer:

Reorder Buffer

Registers

Done?

FP Op Queue

Newest

Oldest

To Memory

Dest

from Memory

Dest

2 ADDD R(F4),ROB1

6 ADDD M[10],R(F6)

Dest

Reservation Stations

FP adders

FP multipliers

ROB7 ROB6 ROB5 ROB4 ROB3 ROB2 ROB1

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17 Tomasulo With Reorder buffer:

Tomasulo With Reorder buffer:

Reorder Buffer

Registers

Done?

FP Op Queue

Newest

Oldest

To Memory

Dest

from Memory

Dest

2 ADDD R(F4),ROB1

Dest

Reservation Stations

FP adders

FP multipliers

ROB7 ROB6 ROB5 ROB4 ROB3 ROB2 ROB1

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18 Tomasulo With Reorder buffer:

Tomasulo With Reorder buffer:

Reorder Buffer

Registers

Done?

FP Op Queue

Newest

F2

DIVD F2,F10,F6

N

F10

ADDD F10,F4,F0

N

Oldest

F0

LD F0,10(R2)

N

To Memory

Dest

from Memory

Dest

2 ADDD R(F4),ROB1

Dest

Reservation Stations

FP adders

FP multipliers

ROB7 ROB6 ROB5 ROB4 ROB3 ROB2 ROB1

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19 Avoiding Memory Hazards

Avoiding Memory Hazards

WAW and WAR hazards through memory are eliminated with speculation because actual updating of memory occurs in order, when a store is at head of ROB, and hence no earlier loads or stores can still be pending RAW hazards through memory are maintained by two restrictions: Not allowing a load to initiate second step of execution if any active ROB entry occupied by a store has a Destination field that matches value of loads A field, and Maintaining program order for computation of effective address of a load with respect to all earlier stores (so (1) can match accurately). These restrictions ensure that any load that accesses a memory location written to by an earlier store cannot access memory until the store has finished

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20 Exceptions and Interrupts

Exceptions and Interrupts

IBM 360/91 invented imprecise interrupts Computer stopped at this PC; its probably close to this address Not so popular with programmers Also, what about virtual memory? (Only in 360/67) Technique for both precise interrupts/exceptions and speculation: in-order completion and in-order commit If we speculate and are wrong, need to back up and restart execution at point where we predicted incorrectly This is exactly what we need to do with precise exceptions Exceptions handled by not recognizing exception until instruction that caused it is ready to commit in ROB If speculated instruction raises exception, record it in ROB This is why reorder buffers in all new processors

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21 Getting CPI Below 1

Getting CPI Below 1

CPI ? 1 if issue only 1 instruction every clock cycle Multiple-issue processors come in 3 flavors: Statically-scheduled superscalar, Dynamically-scheduled superscalar, and VLIW (very long instruction word) 2 types of superscalar processors issue varying numbers of instructions per clock Use in-order execution if statically scheduled, or Out-of-order execution if dynamically scheduled VLIW processors issue fixed number of instructions formatted either as one large instruction or as fixed instruction packet, with explicitly indicated parallelism (Intel/HP Itanium)

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22 VLIW: Very Long Instruction Word

VLIW: Very Long Instruction Word

Each instruction has explicit coding for multiple operations In IA-64, grouping called a packet In Transmeta, grouping called a molecule (with atoms as ops) Tradeoff instruction space for simple decoding Long instruction word has room for many operations By definition, all operations the compiler puts in instruction word are independent => execute in parallel E.g., 2 integer operations, 2 FP ops, 2 Memory refs, 1 branch 16 to 24 bits per field => 7*16 or 112 bits to 7*24 or 168 bits wide Need compiling technique that schedules across several branches

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23 Recall: Unrolled Loop that Minimizes Scalar Stalls

Recall: Unrolled Loop that Minimizes Scalar Stalls

1 Loop: L.D F0,0(R1) 2 L.D F6,-8(R1) 3 L.D F10,-16(R1) 4 L.D F14,-24(R1) 5 ADD.D F4,F0,F2 6 ADD.D F8,F6,F2 7 ADD.D F12,F10,F2 8 ADD.D F16,F14,F2 9 S.D 0(R1),F4 10 S.D -8(R1),F8 11 S.D -16(R1),F12 12 DSUBUI R1,R1,#32 13 BNEZ R1,LOOP 14 S.D 8(R1),F16 ; 8-32 = -24 14 clock cycles, or 3.5 per iteration

L.D to ADD.D: 1 Cycle ADD.D to S.D: 2 Cycles

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24 Loop Unrolling in VLIW

Loop Unrolling in VLIW

Memory Memory FP FP Int. op/ Clock reference 1 reference 2 operation 1 op. 2 branch L.D F0,0(R1) L.D F6,-8(R1) 1 L.D F10,-16(R1) L.D F14,-24(R1) 2 L.D F18,-32(R1) L.D F22,-40(R1) ADD.D F4,F0,F2 ADD.D F8,F6,F2 3 L.D F26,-48(R1) ADD.D F12,F10,F2 ADD.D F16,F14,F2 4 ADD.D F20,F18,F2 ADD.D F24,F22,F2 5 S.D 0(R1),F4 S.D -8(R1),F8 ADD.D F28,F26,F2 6 S.D -16(R1),F12 S.D -24(R1),F16 7 S.D -32(R1),F20 S.D -40(R1),F24 DSUBUI R1,R1,#48 8 S.D -0(R1),F28 BNEZ R1,LOOP 9 Unrolled 7 times to avoid delays 7 results in 9 clocks, or 1.3 clocks per iteration (1.8X) Average: 2.5 ops per clock, 50% efficiency Note: Need more registers in VLIW (15 vs. 6 in SS)

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25 Problems with 1st-Generation VLIW

Problems with 1st-Generation VLIW

Increase in code size Generating enough operations in straight-line code fragment requires ambitious loop unrolling Whenever VLIW instructions arent full, unused functional units translate to wasted bits in instruction encoding Operated in lock-step; no hazard detection HW Stall in any functional unit pipeline caused entire processor to stall, since all functional units must be kept synchronized Compiler might predict functional units, but caches hard to predict Binary code compatibility Pure VLIW => different numbers of functional units and unit latencies require different versions of the code

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26 Intel/HP IA-64 Explicitly Parallel Instruction Computer (EPIC)

Intel/HP IA-64 Explicitly Parallel Instruction Computer (EPIC)

128 64-bit integer regs + 128 82-bit floating point regs Not separate register files per functional unit as in old VLIW Hardware checks dependencies (interlocks => binary compatibility over time) Predicated execution (select 1 out of 64 1-bit flags) => 40% fewer mispredictions? Itanium was first implementation (2001) Highly parallel and deeply pipelined hardware at 800Mhz 6-wide, 10-stage pipeline at 800Mhz on 0.18 process Itanium 2 is name of 2nd implementation (2005) 6-wide, 8-stage pipeline at 1666Mhz on 0.13 process Caches: 32 KB I, 32 KB D, 128 KB L2I, 128 KB L2D, 9216 KB L3

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27 Increasing Instruction-Fetch Bandwidth

Increasing Instruction-Fetch Bandwidth

Predicts next instruct address, sends it out before decoding instruction PC of branch sent to BTB When match is found, predicted PC is returned If branch predicted taken, instruction fetch continues at predicted PC

Branch Target Buffer (BTB)

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28 IF BW: Return Address Predictor

IF BW: Return Address Predictor

Small buffer of return addresses acts as a stack Caches most recent return addresses Call ? Push a return address on stack Return ? Pop an address off stack & predict as new PC

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29 More Instruction-Fetch Bandwidth

More Instruction-Fetch Bandwidth

Integrated branch prediction: branch predictor is part of instruction fetch unit and is constantly predicting branches Instruction prefetch: Instruction fetch units prefetch to deliver multiple instructions per clock, integrating fetch with branch prediction Instruction memory access and buffering: Fetching multiple instructions per cycle: May require accessing multiple cache blocks (prefetch to hide cost of crossing cache blocks) Provides buffering, acting as on-demand unit to provide instructions to issue stage as needed and in quantity needed

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30 Speculation: Register Renaming vs

Speculation: Register Renaming vs

ROB

Alternative to ROB is larger physical set of registers combined with register renaming Extended registers replace function of both ROB and reservation stations Instruction issue maps names of architectural registers to physical register numbers in extended register set On issue, allocates a new unused register for destination (which avoids WAW and WAR hazards) Speculation recovery easy because physical register holding an instruction destination does not become architectural register until instruction commits Most out-of-order processors today use extended registers with renaming

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31 Value Prediction

Value Prediction

Attempts to predict value produced by instruction E.g., loads a value that changes infrequently Useful only if it significantly increases ILP Focus of research has been on loads; so-so results No commercial processor uses value prediction Related topic is address aliasing prediction RAW for load and store or WAW for 2 stores Address alias prediction is more stable and simpler since need not actually predict address values, only whether such values conflict Has been used by a few processors

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32 (Mis) Speculation on Pentium 4

(Mis) Speculation on Pentium 4

% of micro-ops not used

Integer

Floating Point

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33 Perspective

Perspective

Interest in multiple-issue because wanted to improve performance without affecting uniprocessor programming model Taking advantage of ILP is conceptually simple, but design problems are amazingly complex in practice Conservative in ideas, just faster clock and bigger Processors of last 5 years (Pentium 4, IBM Power 5, AMD Opteron) have same basic structure and similar sustained issue rates (3 to 4 instructions per clock) as first dynamically scheduled, multiple-issue processors announced in 1995 Clocks 10 to 20X faster, caches 4 to 8X bigger, 2 to 4X as many renaming registers, and 2X as many load-store units ? performance 8 to 16X Peak vs. delivered performance gap increasing

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34 In Conclusion

In Conclusion

Interrupts and exceptions either interrupt current instruction or happen between instructions Large quantities of state must potentially be saved before interrupting Machines with precise exceptions provide one single point in program to restart execution All instructions before that point have completed No instructions after or including that point have completed Hardware techniques exist for precise exceptions even in the face of out-of-order execution! Important enabling factor for out-of-order execution

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CS136, Advanced Architecture
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