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Clock Skew

Clock Skew. What happens if the clock signals at the source and destination are not in phase? What if the clock arrives at the destination before it reaches the source? Vice-versa? What are the sources of uncertainty in the phase relationship between different clock signals? Clock Skew: pin-to-pin variation in the timing of input clock at each agent (source & destination, in our example) on a bus. The net effect of clock skew is that it can reduce the total delay that signals are allowed to have for a given frequency target. require larger minimum signal delays in order to avoid logic errors. (We’ll cover this in more detail shortly.). Signal Parameters & Timing Class 2. Transmit clock at device a. Receive clock at device b.

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