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State Machine Design
State Machine Design
State Machine Design
State Machine Design
State Machine
State Machine
Parts of a State Machine
Parts of a State Machine
Input Combinational Logic
Input Combinational Logic
Memory
Memory
Output Combinational Logic
Output Combinational Logic
Examples of State Machines
Examples of State Machines
State Machine Design
State Machine Design
State Graphs
State Graphs
State Graphs
State Graphs
Anatomy of a State Graph
Anatomy of a State Graph
State Variables
State Variables
State Variables
State Variables
Output Variables
Output Variables
State Graphs to State Transition Tables
State Graphs to State Transition Tables
State Transition Tables
State Transition Tables
State Transition Tables
State Transition Tables
State Transition Tables
State Transition Tables
State Transition Tables
State Transition Tables
Design Equations
Design Equations
State Machine Design Example
State Machine Design Example
Step 1: Create State Graph (# of States
Step 1: Create State Graph (# of States
Step 2: Determine # of State Variables and Assign
Step 2: Determine # of State Variables and Assign
Step 3: Encode Outputs to States (# Displayed
Step 3: Encode Outputs to States (# Displayed
Step 4: Create State Transition Table
Step 4: Create State Transition Table
Step 5: Write and Simplify Design Equations
Step 5: Write and Simplify Design Equations
Step 6: Circuit Design – AOI Simplified
Step 6: Circuit Design – AOI Simplified
Step 7: Circuit Design – Simplified Further
Step 7: Circuit Design – Simplified Further
Step 8: Circuit Design – Simplified Further XOR
Step 8: Circuit Design – Simplified Further XOR
State Machine Block Diagram / Schematic
State Machine Block Diagram / Schematic

Презентация: «State Machine Design». Автор: DE Revison Team. Файл: «State Machine Design.pptx». Размер zip-архива: 699 КБ.

State Machine Design

содержание презентации «State Machine Design.pptx»
СлайдТекст
1 State Machine Design

State Machine Design

Digital Electronics

© 2014 Project Lead The Way, Inc.

2 State Machine Design

State Machine Design

This presentation will Define a state machine and Illustrate the block diagram for a state machine. Provide several examples of everyday items that are controlled by state machines. Describe the steps in the state machine design process. Provide an example of a state machine design.

2

3 State Machine

State Machine

A synchronous sequential circuit, consisting of a sequential logic section and a combinational logic section, whose outputs and internal flip-flops progress through a predictable sequence of states in response to a clock and other input signals.?

Memory Flip-Flops

Input Combo Logic

Output Combo Logic

Output(s)

Input(s)

Clock

3

4 Parts of a State Machine

Parts of a State Machine

Input Combinational Logic Memory Output Combinational Logic

Memory Flip-Flops

Input Combo Logic

Output Combo Logic

Output(s)

Input(s)

Clock

4

5 Input Combinational Logic

Input Combinational Logic

What should happen next based on the buttons, switches, and other inputs?

Memory Flip-Flops

Input Combo Logic

Output Combo Logic

Output(s)

Input(s)

Clock

5

6 Memory

Memory

Flip-Flops determine the number of states in the design and trigger the state transitions based on the inputs.

Memory Flip-Flops

Input Combo Logic

Output Combo Logic

Output(s)

Input(s)

Clock

6

7 Output Combinational Logic

Output Combinational Logic

What should motors, indicators, and other outputs do once the flip-flops have caused the transition to a new state?

Memory Flip-Flops

Input Combo Logic

Output Combo Logic

Output(s)

Input(s)

Clock

7

8 Examples of State Machines

Examples of State Machines

Many everyday devices are controlled by state machines. Traffic Lights Garage Door Numeric Keypads Vending Machines

8

9 State Machine Design

State Machine Design

Create a State Graph Determine the number of States and label Determine the number of State Variables and label (How many flip-flops needed?) Label Outputs and Encode Outputs to States Create State Transition Table from the State Graph Write and Simplify Design Equations from the State Transition Table Design Circuit

9

10 State Graphs

State Graphs

A state graph shows the sequence of states that the state machine will transition to on each clock transition. This is an example of a state graph with four states (S0-S3).

10

11 State Graphs

State Graphs

Each state “bubble” is labeled (S0,S1,S2,S3). These labels are arbitrary. Each transition arc is labeled with the values of the input variables that make the transition occur.

11

12 Anatomy of a State Graph

Anatomy of a State Graph

Transition Arc (For Input X=0) Hold State

Input Variable (X)

State (S0)

State “Bubble”

Transition Arc (For Input X=1) Next State

State Variables (Qa & Qb)

Next State “Bubble”

Output Variables (Y & Z)

12

13 State Variables

State Variables

The state variables are actually the outputs of the memory flip-flops. For that reason they are typically labeled Qa, Qb, etc.

S0

This four state example would require (2) flip-flip (Qa and Qb) to clock through four states (S0-S3). 1st State (SO) Qa Qb = 0 0 2nd State (S1) Qa Qb = 0 1 3rd State (S2) Qa Qb = 1 0 4th State (S3) Qa Qb = 1 1

Qa Qb 0 0

13

14 State Variables

State Variables

If a 5th state was needed: Can you guess how many flip-flops and state variables you would need? (It is not possible to have exactly 5 states) How many states would go un-used?

1st State (SO) Qa Qb = 0 0 2nd State (S1) Qa Qb = 0 1 3rd State (S2) Qa Qb = 1 1 4th State (S3) Qa Qb = 1 1 5th Sate (S4) ??????? = ?????

14

15 Output Variables

Output Variables

Each state “bubble” is assigned output variables. This example has 4 output variables based on what state it is in.

15

16 State Graphs to State Transition Tables

State Graphs to State Transition Tables

16

17 State Transition Tables

State Transition Tables

State Transition Tables are then created from the State Graph. They describe the Present State (inputs) and the Next State (outputs) associated with each state (S0-S3).

17

18 State Transition Tables

State Transition Tables

Notice that each state occupies 2 lines on the State Transition Table. That is because (in this example) each transition is triggered by only one of 4 possible inputs at any time. For: Input that causes transition: S0 OS = 0 ;OS = 1 S1 OL = 0 ;OS = 1 S2 CS = 0 ;CS =1 S3 CL = 0 ;CL = 1

18

19 State Transition Tables

State Transition Tables

In a state machine, the Next State is actually the output from the Memory flip-flops (Qa* Qb*) when an input is changed. Qa* = Da for the next state on one flip-flop and Qb* = Db for the next state on the other flip-flop

19

20 State Transition Tables

State Transition Tables

The outputs from the Memory flip-flops are linked to the Input Combinational Logic. That way a transition is made on the next clock signal to the next state.

Qa* = Da for the next state on one flip-flop and Qb* = Db for the next state on the other flip-flop

Memory Flip-Flops

Input Combo Logic

Output Combo Logic

Output(s)

Input(s)

Clock

20

21 Design Equations

Design Equations

From the State Transition Table you can now determine the un-simplified expressions for the: Input Combinational Logic Da=Qa* Db=Qb* Output Combinational Logic This example has (4) outputs MO – Motor Open Signal MC – Motor Close Signal GO – Gate Open Indicator GC – Gate Closed Indicator

21

22 State Machine Design Example

State Machine Design Example

Design a state machine that will count out the last four digits of a phone number ONLY when an Enable pushbutton is pressed. The output should hold the last number until the Enable button is pressed again. (Example 585-476-4691) Whenever the Enable is a logic (1), the outputs will continuously cycle through the four values 4,6,9,1. Whenever the Enable is a logic (0), the outputs will hold at their current values. For this design any form of combinational logic may be used, but the sequential logic must be limited to D flip-flops.

22

23 Step 1: Create State Graph (# of States

Step 1: Create State Graph (# of States

EN = 0

EN = 1

EN = 1

EN = 0

EN = 0

EN = 1

EN = 1

EN = 0

23

24 Step 2: Determine # of State Variables and Assign

Step 2: Determine # of State Variables and Assign

EN = 0

EN = 1

EN = 1

EN = 0

EN = 0

EN = 1

EN = 1

EN = 0

24

25 Step 3: Encode Outputs to States (# Displayed

Step 3: Encode Outputs to States (# Displayed

EN = 0

EN = 1

EN = 1

EN = 0

EN = 0

EN = 1

EN = 1

EN = 0

25

0100 C3=0 C2=1 C1=0 C0=0

1001 C3=1 C2=0 C1=0 C0=1

0001 C3=0 C2=0 C1=0 C0=1

0110 C3=0 C2=1 C1=1 C0=0

26 Step 4: Create State Transition Table

Step 4: Create State Transition Table

State

State

State

State

State

State

Inputs

Inputs

Inputs

Outputs

Outputs

Outputs

Outputs

Outputs

Outputs

Outputs

Outputs

Qa

Qb

EN

Qa*

Qb*

Da

Db

C3

C2

C1

C0

S0

0

0

0

S0

0

0

0

0

0

1

0

0

S0

0

0

1

S1

0

1

0

1

0

1

0

0

S1

0

1

0

S1

0

1

0

1

0

1

1

0

S1

0

1

1

S2

1

0

1

0

0

1

1

0

S2

1

0

0

S2

1

0

1

0

1

0

0

1

S2

1

0

1

S3

1

1

1

1

1

0

0

1

S3

1

1

0

S3

1

1

1

1

0

0

0

1

S3

1

1

1

S0

0

0

0

0

0

0

0

1

See Slide Notes for a detailed description

Present State

Present State

Input

Next State

Next State

F/F Inputs

F/F Inputs

Encoded Outputs

Encoded Outputs

Encoded Outputs

Encoded Outputs

26

27 Step 5: Write and Simplify Design Equations

Step 5: Write and Simplify Design Equations

27

28 Step 6: Circuit Design – AOI Simplified

Step 6: Circuit Design – AOI Simplified

Can you think of a better way to impliment the logic for Db ?

28

29 Step 7: Circuit Design – Simplified Further

Step 7: Circuit Design – Simplified Further

29

30 Step 8: Circuit Design – Simplified Further XOR

Step 8: Circuit Design – Simplified Further XOR

30

31 State Machine Block Diagram / Schematic

State Machine Block Diagram / Schematic

31

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